The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop (hereinafter, referred to as “DLL”) circuit of the semiconductor memory device.
In a system equipped with a plurality of semiconductor devices for performing various functions, a semiconductor memory device functions as an apparatus for storing data. The semiconductor memory device outputs data, which are corresponding to the address signals inputted from a data processing unit (e.g., a central processing unit) to a device that requests the data, or stores data delivered by the data processing unit in unit cells corresponding to the address signals which are inputted together with the data.
The operating speed of systems is getting faster and faster. Therefore, semiconductor memory devices need to have fast input and output speed in the data processing unit. Recently, the operating speed of the data processing unit has been increasing; however, semiconductor memory devices that deliver the data to the data processing unit have not kept pace.
In order to enhance the data I/O speed of the semiconductor memory device, various semiconductor memory devices have been developed. Synchronous memory devices in which the data is inputted and outputted in response to system clock signals have been proposed. The synchronous memory devices output the data to the data processing unit in response to the inputted system clock signals and also receive the data from the data processing unit in response to the inputted system clock signals. However, since the synchronous memory devices are unable to follow the operating speed of the data processing unit, DDR synchronous memory devices have been developed. The DDR synchronous memory devices input and output the data in response to a transition time of the system clock signal. More specifically, in the DDR synchronous memory devices, the data is inputted and outputted in synchronization with rising and falling edges of the system clock signal.
However, the system clock signal inputted into the semiconductor memory device reaches a data output circuit, inevitably resulting in a delay time which is caused by both a clock input buffer disposed within the memory device and a transmission line to transmit the clock signal thereto. Therefore, when the data output circuit outputs the data in synchronization with the system clock signals which already have such a delay time, an external circuit which receives the output data from the semiconductor memory device may take them in asynchronization with the rising edge and the falling edge of the system clock signal.
To solve this problem, the semiconductor memory device includes a delay locked loop for locking an amount of the delay time of the clock signal. The delay locked loop is a circuit that compensates for the delay time caused by the internal circuits in the memory device until the system clock signal is delivered to the data output circuit after being inputted to the memory device. The delay locked loop finds an amount of the delay time of the system clock signal which is caused by delay circuits, such as the input buffer and the clock signal transmission line, and delays the system clock signal based on the delay amount which has been found. The delay locked loop outputs the delayed system clock to the data output circuit. Thus, the system clock signal inputted into the memory device is delivered to the data output circuit with a fixed delay time by the delay locked loop. The data output circuit outputs the data in synchronization with the delay locked clock signal and the external circuit regards the output data as the normal data which is accurately outputted in synchronization with the system clock signal.
In operation, the delay locked clock signal outputted by the delay locked loop is transferred to an output buffer at a point of time which is determined faster than the data output time by one period of time and the data is outputted in synchronization with the transferred delay locked clock signal. As a result, the data is more rapidly outputted than the amount of delay time of the system clock signals caused by the internal circuits of the memory device. In this way, it seems to the external circuit of the memory device that the data is accurately outputted in synchronization with the rising edge and the falling edge of the system clock signal. In conclusion, the delay locked loop is a circuit to find delay value to compensate for the delay time of the system clock signal within the memory device, thereby achieving the fast data output operation.
When the data is outputted in synchronization with the delay locked clock signal from the delay locked loop circuit, the circuit to receive the data can exactly receive them in synchronization with the system clock signal. However, since the delay locked clock signal has a constant frequency, there may be a problem in that an EMI (Electromagnetic Interference) characteristic deteriorates during the data transmission process. If a clock frequency employed when the data is received and transferred between the semiconductor memory device and the data processing apparatus is fixed to one constant frequency, the EMI characteristic may deteriorate. To solve the problem, a system equipped with the semiconductor memory device has a SSC (Spread Spectrum Clock) function. The SSC function is to disperse the power spectrum by modulating the clock signal from the semiconductor memory device. However, when the SSC function does not work appropriately, the EMI characteristic deteriorates because the power spectrum of the clock signal from the semiconductor memory device is distributed with a peak.